MemTest86 Version History
On this page you can find a summary of all the changes that have been made in each version of MemTest86.
Version 7.5 (Build 1001) 21/Feb/2018
- Fixed AP being reset after every memory segment causing tests to slow down significantly for some systems
Version 7.5 5/Feb/2018
- Added check for whether the number of errors exceed a maximum error count. If so, the tests are aborted. This can be configured via the configuration file parameter MAXERRCOUNT. By default the value is 10000
- Added support for Russian language
- Added new configuration file parameter EXITMODE for specifying whether to shutdown or reboot the system on exit
- Added support for reporting to Management Console (https://www.passmark.com/products/bitmgtconsole.htm) via XML messages over TFTP (Site Edition only). The status of MemTest86 is periodically reported to the management console
- Added new configuration file parameter TFTPSERVERIP for specifying a different TFTP server IP address for sending report files and reporting to the management console (Site Edition only)
- Added workaround for retrieving configuration files from TFTP servers that don't support the 'get file size' TFTP command (Site Edition only)
- Added workaround for Serva bug when overwriting a file on the TFTP server (Site Edition only)
- Fixed bug with generated HTML/XML files that require character escaping
- Added workaround when firmware EFI_GET_TIME function fails to retrieve the time correctly. A warning is also written to the log file
- Added new flag DISABLE_CONCTRL to blacklist for console control workarounds for older firmware
- Fixed 'ALL' BIOS versions not being parsed properly in blacklist
- Updated blacklist.cfg file with additional baseboards with known issues
- Added more robust detection of CPU hyperthreads
- Added ECC detection support for Intel Skylake-SP chipsets
- Added ECC detection/injection support for AMD Ryzen chipsets. Note that injection support is typically disabled by AMD, except for some CPUs which are engineering samples.
- Added warning message to log file when ECC injection is locked on Atom C2000 chipsets
- Fixed bug with ECC error reporting on Intel Xeon E3 chipsets
- Fixed CPU temperature not being shown for Intel Apollo Lake, Skylake-X and Broadwell-E chipsets
- Added preliminary support for retrieving CPU info for Intel Cannon Lake/Knights Mill chipsets
- Fixed bug with retrieving the number of boosted P-states in AMD chipsets
- Fixed CPU temperature not being read properly on AMD 15h (model >= 40h) chipsets
Version 7.4 26/July/2017
- Added new file blacklist.cfg that contains a list of baseboards that have known MemTest86 boot issues
- Added 'CONSOLEMODE' config file parameter for specifying the mode of the UEFI console. Setting the console mode determines the resolution of the console (with 0 being the minimum supported resolution of 80x25)
- Added 'BITFADESECS' config file parameter for specifying the sleep interval in the Bit Fade test (Test 10)
- Added language support for Catalan
- Updated ImageUSB to version 1.3
- Fixed 128-byte alignment issues in the random library
- Errors detected in Test 12 (128-bit Random Number Sequence Test) are now logged as 128-bit values
- HTML test report now includes if ECC polling was enabled
- Fixed text artifacts appearing in the testing screen due to the text being too long
- Fixed memory size being incorrectly reported due to including non-RAM memory ranges (eg. NVM, MMIO, Reserved)
- Fixed main menu screen being too small due to resolution being set too high
- Added preliminary ECC Injection support for Intel Xeon E5 chipsets
- Added preliminary ECC Injection support for Intel D-1500 chipsets
- Added ECC detection support for different variations of Intel Kaby Lake chipset
- Added support for retrieving AMD Ryzen CPU info, including base and turbo clock speeds
- Improved the performance and robustness of measuring CPU base/turbo speeds for AMD chipsets
- Updated JEDEC RAM manufacturer ID list
- Added reset mechanism for Intel ICH SMBus when timeout occurs while accessing SPD registers
- Fixed DDR4 SPD data not being read for PIIX4 SMBus controllers
Version 7.3 27/Feb/2017
- CPU cores that are identified as hyperthreads are now disabled by default, due to minimal performance benefits
- Fixed potential system hang caused by memory alignment issues when allocating 128-bit variables on the stack during the 128-bit random number sequence test (Test 12)
- Improved performance of the 128-bit random number sequence test (Test 12) by using SSE2 comparison intrinsics
- Improved performance of the row hammer test (Test 13) by increasing the default step size to 0x1000000 (16MB) for subsequent passes after the first pass. On the first pass, the default step size is 0x4000000 (64MB)
- Reduced test time of the row hammer test (Test 13) by using only a single offset bit to determine the row address pair, rather than cycle through all possible offset bits.
- Added 'ENABLEHT' config file parameter to enable/disable CPU cores identified as hyperthreads
- Added 'HAMMERSTEP' config file parameter to specify the step size for the next row pair to hammer in the row hammer test (Test 13). Increasing the step size reduces the memory test coverage, but will also decrease the test time. By default, the step size is 0x1000000 (16MB)
- Added several known baseboards to to a 'blacklist' of boards that have known issues when running in multiprocessor mode. If a blacklisted baseboard is detected, the Multiprocessor test is skipped during startup and the CPU selection mode is set to single.
- Fixed triggering of ECC error injection on Intel Skylake (Xeon E3 v5) chipset
- Added ECC detection and injection support for Intel KabyLake (Xeon E3 v6 family) chipsets
- Added ECC detection and injection support for Apollo Lake SoC (Atom E3900 Series) chipsets
- Added support for retrieving RAM SPD data on Intel Skylake-E chipsets
- Fixed issue with the test elapsed time having strange values when running in round robin or sequential CPU mode due to the timestamp counter not being synchronized on the CPU cores
Version 7.2 13/Dec/2016
- Language support for Italian
- Added ECC detection support for Broadwell-H chipsets
- Added ECC injection support for Broadwell-H chipsets
- Added ECC detection support for AMD Merlin Falcon
- Added fix for certain Intel Xeon E5 platforms that are unable to access the ECC and SMBus registers
- TSOD polling is now temporarily disabled on Intel E5 v3 platforms when reading SPD bytes. Previously, this caused invalid bytes to appear in the SPD data.
- Added sanity check for invalid characters in the SPD part number string
- Updated JEDEC ID manufacture names
- Fixed crash when the number of processors is greater than the max supported (120)
- Added SMBIOS system, baseboard and BIOS info to MemTest86 reports
- Reduced the number of decimal points when displaying memory/cache speeds
- Added workaround for certain UEFI firmware when setting console resolution
- Report file name is now prepended with the baseboard serial number when running MemTest86 Site Edition in order to distinguish from reports from other machines
- Added "Mac-F42C88C8" to a blacklist of known unsupported baseboard/EFI firmwares. When a blacklisted baseboard/EFI firmware is detected, a warning message is displayed.
- Updated to latest UDK + compiler tools
- Various system info related updates/fixes (CPU)
Version 7.1 5/Aug/2016
- Fixed a bug in measuring CPU clock speed using HPET which could skew the clock speed results to unreasonable values. This may have caused issues during startup including extremely long loading times
- Added fallback mechanism to use the legacy PIT to measure the clock speed if the measured CPU clock speed using HPET is unreasonable
- Disabled code optimization for Test 12 due to reported freeze when running in parallel mode
- Fixed CPU selection mode not being set according to the results of the multiprocessor test during startup
- When switching to the next target CPU in Sequential/Round Robin mode, attempt to reset the target CPU if there was a failed attempt to switch the BSP
- When looking for SMBus devices for RAM SPD retrieval, attempt to look for any disabled SMBus devices to enable before enumerating the PCI bus
- Fixed cursor appearing for some systems during testing
Version 7.0 20/July/2016
- Row Hammer Test (Test 13) now uses double-sided hammering and random data patterns in an attempt to expose more RAM modules susceptible to disturbance errors.
- PXE network boot is now fully supported (MemTest86 Site Edition only) to support scalable, diskless deployment to PXE-enabled clients. Like the Pro version, the configuration file (acquired from the PXE server via TFTP) can be used for customization and configuration of MemTest86 memory tests. Report files can also be uploaded to the server. Logging, however, is unavailable.
- Memory tests are run in Parallel CPU mode by default, if supported by the UEFI firmware. Running in parallel mode significantly decreases the test time as compared to running in single CPU mode and should also help to detect more errors faster. This was made possible after developing a work around for UEFI BIOS bug that prevented multi-threading on some machines.
- Added 'HAMMERPAT' config file parameter to specify the data pattern to use for the row hammer test. By default, random data patterns are used.
- Added 'HAMMERMODE' config file parameter to specify whether to use single or double sided hammering. By default, double-sided hammering is used.
- Added 'CPULIST' config file parameter to specify a subset of available CPUs to enable for the memory tests.
- Added 'DISABLEMP' config file parameter to disable multiprocessor support in MemTest86. This can be used as a workaround for certain UEFI firmwares that have issues running MemTest86 in multi-CPU modes.
- Added 'BGCOLOR' config file parameter to specify the background colour to use
- Added Portuguese translations
- Added Czech translations
- Added ECC support for different revisions of Intel Skylake memory controllers
- Fixed ECC detection on Intel Broadwell-H chipsets
- Changed how ECC errors are detected on Broadwell chipsets
- Changed how ECC errors are detected on Atom C2000 chipset
- Fixed incorrect channel/slot number being reported for ECC errors on E5 chipsets
- Added SMBUS (SPD) support for Intel Broxton
- Added SMBUS (SPD) support for Intel Airmont
- Added SMBUS (SPD) support for Intel Sunrise Point-LP
- Reduced the number of iterations for the Modulo 20 Test (Test 9) to decrease the test time
- Reduced the number of addresses to be hammered for the Row hammer Test (Test 13) to decrease the test time
- When no tests are completed, the test report now displays "N/A" as oppose to "PASS"
- The High Precision Event Timer (HPET) is now used to measure the clock speed, if available. Otherwise, the older Programmable Interval Timer (PIT) is used.
- The clock speed displayed in the RAM info is now the effective clock speed as opposed to the actual clock speed. The effective clock speed is twice the actual clock speed for DDR RAM.
- Speeds greater than 10000MB/s are converted to GB/s when displaying memory/cache speeds in the test screen
- Memory sizes greater than 10240MB are now displayed in GB
- Console is no longer forced to 80 x 25 if the current mode has a higher resolution
- Fixed issue with certain UEFI firmware when switching from console to graphics mode
- Fixed RAM benchmark chart title string overflow
- Various system info related updates/fixes (CPU)
Version 6.3.0 27/Jan/2016
- New configuration file parameters MINSPDS, SPDMANUF and SPDPARTNO to specify the values that the RAM SPD must match before allowing the tests to start. This may be useful for RAM manufacturers that need to verify that the SPD data has been programmed correctly.
- New configuration file parameter SKIPSPLASH to skip the 10 second splashscreen and proceed directly to the main menu
- New mode for the configuration file parameter AUTOMODE to specify that MemTest86 shall run the tests immediately (skipping the splashscreen and main menu) but prompt the user to save the results after test completion
- New configuration file parameters ADDR2SLBITS and ADDR2CSBITS to specify the bit positions of a memory address to exclusive-or (XOR) to determine which DIMM slot/chip select (0 or 1) corresponds to the failure address
- Added ECC detection support for Broadwell-H chipset
- Added ECC detection support for Broadwell-DE chipset
- Added ECC detection support for AMD Bald Eagle (2nd generation Embedded R-series)
- Added ECC injection support for AMD Steppe Eagle/Bald Eagle
- Added SMBus (SPD) support for Broadwell-DE
- Fixed decoding of JEDEC manufacture names from the SPD
- DDR3 XMP rev1.3 SPD decoding is now supported
- Fixed retrieval of DDR4 SPD bytes for Intel ICH SMBUS
- Added workaround for buggy firmware when calls to EFI MPServices fail
- Fixed MemTest86 freezing on network boot
- Fixed bug with wrong details being displayed for detected memory warnings in the report file
- Fixed bug with CPU type detection for older CPUs
- Fixed benchmark chart not being displayed after running a RAM benchmark test when there is a failure in saving results to disk
- Report file now includes the RAM serial number, if available
- Various system info related updates/fixes (CPU)
Version 6.2.0 8/Sept/2015
Due to the high number of failures reported for the Hammer Test (Test 13), the algorithm was revised to perform 2 potential passes:
- Row pairs are hammered at the maximum hammer rate. (ie. no delays between each row pair hammer)
- Row pairs are hammered at a lower hammer rate (200K per 64ms, as determined by memory vendors as the worst case scenario)
- If memory errors are detected in the first pass, error details are not immediately displayed to the user and the second pass is started. If errors are detected in the second pass, they are reported as normal.
- If errors are detected in the first pass but not the second pass, a warning of potential high frequency bit flips is displayed to the user.
- The premise behind this revision is to better inform users of the significance of errors detected in the Hammer Test, as opposed to a strict PASS/FAIL result. Although errors detected in this test are real errors, the conditions needed to induce these errors occur only very rarely in normal PC usage, and should not be of concern to most users. Therefore, a warning rather than an outright failure would ensure the user is aware of the issue and be able to take the necessary measures to mitigate the issue.
- The details of the errors that were detected in the first pass of the Hammer Test but not during the second pass can be displayed in the report by specifying the configuration file parameter 'REPORTNUMWARN'. This parameter represents the maximum number of warnings to display in the report file.
New configuration file parameter 'AUTOMODE' for full automation. Enabling this parameter shall result in the following:
- Splash screen is skipped and the tests are started immediately
- When the tests are completed, the report is saved to disk automatically
- System is rebooted
- Shortened the test time for Hammer Test (Test 13) by reducing the total number of hammers per row address pair
- Fixed issue with the main menu not displaying for certain EFI firmware. Due to the fact that many EFI firmwares require the use of the obsolete ConsoleControl protocol to switch between graphics/console mode, the graphics/console mode workaround is now enabled by default.
- Fixed bug with details of empty RAM slots being displayed when using SMBIOS memory device information
- Added Intel Skylake ECC support
- Updated Jedec manufacturer ID list for displaying the vendor name from RAM SPD. Fixed Jedec manufacturer ID lookup function to support > 7 continuation codes.
- Fixed AMD Hudson-2/Hudson-3 SMBus support to include various hardware revisions
- Various system info related updates/fixes (SPD, CPU)
Version 6.1.0 5/June/2015
- New config file parameter REPORTNUMERRS for specifying the maximum number of errors to include in the report
- Language support for Spanish
- RAM details obtained from SMBIOS are now displayed if SPD information cannot be accessed
- Added ECC detection support for Intel Atom C2000 SoC chipset
- Added ECC injection support for Intel Atom C2000 SoC chipset
- Added ECC injection support for Intel Xeon E3 (Sandy Bridge/Ivy Bridge) chipset (untested)
- Added SMBus (SPD) support for Intel 5100 chipset
- Added SMBus (SPD) support for Intel Wildcat Point chipset
- Added SMBus (SPD) support for Intel Sunrise Point chipset
- Improved speed of retrieving SPD data
- Fixed potential issue with retrieving DDR4 SPD due to the bank address not being restored back to its original value
- Fixed decoding of ECC support in DDR2 SPD
- Added support for more precise timings supported by DDR3 rev 1.1 and later
- Fixed bug with retrieving SPD details for a large number of RAM modules (ie. > 16)
- Fixed the progress indicator for Test 13 (Row hammer test) to be more linear
- Reduced the test time for Test 13 (Row hammer test)
- Fixed the displayed error details when ECC errors are detected
- Fixed freeze while initializing the screen for some firmwares due to an unsupported driver protocol
- Added workaround for incorrect text length/height returned by the UEFI firmware
- Added checks for the number of cores exceeding the maximum supported in MemTest86
- Synchronized cache enabling/disabling across all CPUs
- Migrated CPU cache info code from PerformanceTest/BurnIn Test. The displayed cache info should now be more consistent with what is displayed in BurnIn Test/Performance Test.
- Fixed Enabling/Disabling of features in the Sys Info screen to be less confusing
- Fixed CPU Selection screen to truncate the list of available processors when more than 16 are available
- Various system info related updates/fixes (CPU)
Version 6.0.0 13/Feb/2015
- Support for DDR4 RAM (and associated hardware), including retrieval and reporting of DDR4-specific SPD details. This includes DDR4 RAM that support Intel XMP 2.0 DDR4 RAM timings.
- New RAM benchmarking feature allowing results to be graphed and saved to disk. Previous results can be graphed on the same chart for comparison.
- New "Hammer Test" for detecting disturbance errors caused by charge leakage when repeatedly accessing addresses in the same memory bank but different rows in a short period of time.
- Language support for French/German/Japanese/Chinese. All text are displayed in the selected language, including generated reports.
- Added Haswell-E CPU (DDR4) ECC support
- Added Xeon E5 v3 ECC support
- Added Ivy Bridge CPU (non-Xeon) ECC support
- Added AMD Steppe Eagle CPU ECC support
- Added Intel Atom E3800 SoC ECC support
- Fixed ECC detection for Ivy Bridge-EX / Haswell-EX chipsets that have a 2nd memory controller
- Fixed Intel 5400 ECC registers not being reset after starting test
- Fixed ECC errors immediately being reported after starting test (Ivy Bridge-E)
- Added support for ECC injection for Intel Xeon E3 v3 (untested)
- Fixed handling of Intel ICH SMBUS built-in hardware semaphore to prevent SMBus device contention
- Fixed possible crash when DDR3 module type value in the RAM SPD info is invalid
- Fixed DDR4 SPD clock speed rounding errors in the RAM SPD info
- Fixed DDR3 SPD Register manufacturer/type in the RAM SPD info not appearing correctly
- CPU speed measurement is now more robust by taking multiple samples
- Fixed Intel turbo clock speed calculation
- Fixed detection of Intel turbo support for Xeon chipsets
- Increased maximum # of supported CPUs to 72
- Increased maximum # of supported RAM modules to 64
- Increased the number of supported memory controllers to 8
- New config file parameter 'ECCINJECT' for specifying whether to enable/disable ECC injection
- New config file parameter 'MEMCACHE' for specifying whether to enable/disable memory caching
- New config file parameter 'PASS1FULL' for specifying whether the first pass should run the full iteration or reduced iteration
- New config file parameter 'ADDR2CHBITS' to specify the address bits to XOR to determine the memory channel
- New config file parameter 'LANG' for specifying language to use on startup
- Console resolution is now forced to 80 x 25
- Graphics resolution is now set to a minimum of 1024 x 768
- Updated ImageUSB to v1.1.1015 which includes an option to zero the USB drive. This is useful to recover Flash drive capacity
- Running memory tests in parallel mode is now more robust for UEFI BIOS that exhibit inconsistent multiprocessor behaviour
- Fixed detection of the number of enabled processors for UEFI BIOS that exhibit inconsistent multiprocessor behaviour
- Fixed test status screen not being displayed correctly for consoles with small/large screen widths
- In the RAM SPD menu screen, PGUP/PGDN can be used to navigate between pages of RAM modules
- For specific cases where files under EFI\BOOT cannot be accessed (eg. grub2), log/report files shall be written to the root directory
- During MemTest86 boot-up, the system memory map is now written to log file for debugging purposes
- Various optimizations of the size of the MemTest86 binary
- Forced a memory address limit of 32-bits when running under 32-bit UEFI, fixing an 32bbit overflow bug on some systems
- Memory ranges to be tested are now allocated at the beginning of each test (due to the possibility that the memory map changes in the middle of testing)
- Reduced the number of log messages written when waiting for other processors to finish when running in parallel mode
- When allocating memory for Bit Fade Test, leave 1MB of free memory available (to prevent firmware drivers from running out of memory)
- Fixed potential crash or other unexpected behaviour due to memory issues with random functions
- Reports are now saved using UTF16 encoding to support Unicode characters
- Changed memory allocation behaviour by only pre-allocating memory segments >= 16MB to prevent memory starvation
- MemTest86 is code signed by Microsoft. Allowing support for secure boot (like V5). But V6 now uses a extended validation (EV) certificate.
Version 5.1.0 16/May/2014
- Fixed ECC error detection for Ivy Bridge-E chipsets
- Fixed rounding of memory SPD timings
- On 32-bit systems, systems with upper address limit > 32-bits freezing during testing is now fixed
- Locking memory for testing is now more robust
- Added SPD support for VT8237S, Intel X79, Intel NM10 Chipsets
- Fixed incorrect decoding of # of banks in DDR2 FB SPD causing the memory stick size to be reported incorrectly
- Increased the number of supported memory modules from 16 to 32
- Increased the maximum number of SMBus controllers to 8
- DDR3 revision 1.3 SPD decoding now supported
- Fixed SMBUS CLK issues when retrieving SPD details for Intel chipsets
- CPU spec updates, AMD Kaveri + Intel Haswell refresh
- Xeon (Ivy Bridge and later) non-Turbo CPU speeds now recorded.
- Minor temperature reporting changes for AMD Family 15h, Models 0h-0Fh and 30h-3Fh (e.g. A10-7850K)
- Fixed "Pass" progress bar so that it shows 100% on completion of one pass
- A notification text is now displayed when ECC errors are injected
- Improved notificaion text displayed when ECC errors are detected
- Updated MemTest86 BIOS version to 4.3.7
Version 5.0 release for UEFI 3/Dec/2013
- Completely re-written to work under UEFI.
- Native 64-bit support
- No longer requires the use of the PAE workaround to access more than 4GB of memory. (PAE = Physical Address Extension)
- Mouse support, where supported by the underlying UEFI system. On older systems a keyboard is still required.
- Improved USB keyboard support. The keyboard now works on systems that fail to emulate IO Port 64/60 correctly. So Mac USB keyboards are now supported.
- Improved multi-threading support, where supported by the underlying UEFI system.
- Dual boot with Memtest version 4 for supporting older systems without UEFI. So with a single USB or CD drive both UEFI systems and BIOS systems can be supported.
- Reporting of detailed RAM SPD information. Timings, clock speeds, vendor names and much more.
- Support to writing to the USB drive that Memtest is running from for logging and report generation. In all prior MemTest releases there was no disk support.
- Use of GPT. (GUID Partition Table)
ECC RAM support (limited hardware support, ongoing development)
- Detection of ECC support in both the RAM and memory controller
- Polling for ECC errors
- Injection of ECC errors for test purposes. (limited hardware only)
- Option to disable CPU caching for all tests
- Support for reading parameters from a configuration file to allow settings to be predefined without the need for keyboard input. This can help with automation.
- Support for Secure Boot
- Speed improvements of between 10% and 30%+. Especially for tests, #5, #8 & #9. This is the result more moving to native 64bit code, removing the PAE paging hack, switching compilers and using faster random number generation algorithms.
- Addition of 2 new memory tests to take advantage of 64bit data and SIMD instructions.
Version 4.3.7 13/May/2014
- Fixed freeze (particularly for older machines) caused by incorrect handling of RSDP revision 0 in the multiprocessor detection code.
- Added menu option for enabling serial console mode.
Version 4.3.6 14/Nov/2013
- Fixed crash (particularly for AMD machines) that is seemingly resolved by adding CPU synchronication barriers before and after performing the memory speed test
- Fixed an error in setting the barrier structure's base address, preventing a possible crash or freeze of the system.
- Added a check to perform a spin lock only when more than 1 CPUs are detected
Version 4.3.5 24/Oct/2013
- Fixed potential error due to barrier structure located at fixed memory location
- Fixed block move test freeze on higher memory addresses
Version 4.3.4 2/Oct/2013
- Fixed incorrect progress calculation for test 0
- Fixed incorrect memory size due to bug with memory map when the e820 entry size member is 0
- Fixed incorrect number of CPU's found due to duplicate entries in the MADT
- Changed the method used to search for processors to searching the APIC MADT first, then search the MP spec table (as opposed to vice versa). The MP spec table has largely been deprecated.
Version 4.3.3 11/Sept/2013
- Fixed incorrect progress calculation for test 4
- Fixed potential false positives in parallel mode caused by overlapped/unaligned memory chunk allocations per CPU
- Fixed program freeze when selecting test 0 or 1 when running in non-parallel mode
Version 4.3.2 22/Aug/2013
- Memory bandwidth is now measured for one CPU (as opposed to being a total for all CPUs & Cores). This will lower the reported bandwidth for multi-core machines. But we think it makes more sense this way.
- Fixed crash when attempting to boot on older single core machines with hyperthreading. Only effects old machines, from around the early Pentium 4 era, that didn't have a MP (Multi-Processor) Spec table defined but did have both a MADT (Multiple APIC Description Table) defined and hyperthreading enabled.
- Restored the "Start only one CPU" boot option. This option should not be required in normal use, but might be useful for debugging purposes.
- Updates to the included help file
Version 4.3.1 8/Aug/2013
- Fixed bug with Test 6 (Block Move Test) not testing the end of a memory segment correctly. This bug could have resulted in false errors being reported in Test #6. The false errors were rare in normal use, but could be provoked more easily by running the tests out of order. e.g. running Test #1, then Test #6.
- Removed unnecessary boot options in menu
Version 4.3.0 10/Jul/2013
- Changed default CPU selection mode to round robin. Running all CPUs at once has been shown to cause false positives on a number of systems.
- Fixed a bug that could cause the program to go into a tight loop that could not be escaped when setting certain memory ranges to test.
- Fixed a bug displaying the memory location of individual errors. The values after the decimal point in the MB readout were incorrect.
- Fixed a bug in configuring upper and lower memory limits, previously lower limits equal or grater than 2gb would not work, as well as some other more obsucre configurations.
- Added a misc option to display the systems memory map.
- Fixed a bug that would cause the number of passes to not correctly reset after changing the selected tests.
- Added missing source code to some of the download packages.
- Fixed a bug in test 8 causing a single error to cascade into multiple errors.
- Fixed a bug causing the average error bits to be incorrect once the errors had maxed out at 65k
- Fixeda bug preventing test 10 to be selected as a single test to run.
- Fixed bug displaying individual test error counts.
- Fixed bug making overall errors 10x what they should be.
Version 4.2.0 18/Mar/2013
- Fixed issues with USB keyboards. The USB keyboard functionality is memory mapped into a portion of low memory on some (maybe many) machines, typing on a USB keyboard changes some values in RAM as the key presses are stored in memory as you type. This can cause the keyboard to become unresponsive during testing or input from the keyboard to generate errors in the tests.
- Fixed crash when configuring memory ranges. Changing the meory range during the first test, or changing the memory range multiple times during later tests could cause the current test number to become negative, triggering a crash.
- Fixed highest error address not reporting correctly on error.
- Fixed error counters overflowing and reseting to 0 after too many errors.
- Fixed max contiguous error reporting.
- Cleaned up some UI text.
- The Windows USB package now includes ImageUSB to make creating Memtest86 USB drives easier.
Version 4.1.0 Jan/2013
Added a new boot trace option that single steps through the testing process
and displays messages and data that is valuable in diagnosing problems with
test execution. A large number of trace points have been added in key portions
of the code (in particular SMP startup routines) to provide visibility of
obscure failures. This feature will allow non-technical users to provide
troubleshooting data for better test stability.
Added a new One Pass feature. This feature runs the complete test once and
then exits, but only if there were no errors. This provides a convenient
method for unattended testing. One Pass may be enabled via a boot option or
via an on-line command.
Images for CD, USB key and Floppy disks now use Syslinux for booting and
include a variety of standard options and two previous versions of MemTest86.
The new boot time options may be specified at the boot prompt.
A feature has been added to allow customization of the list of tests to be
run. The test list may be specified via a boot option or via an on-line
A feature has been added to restrict specific CPUs that are to be used for
testing. The maximum number of CPUs may be specified or a 32 bit CPU mask may
be specified. These are enabled with boot options.
A number of problem with use of on-line commands when testing with more
than one CPU have been fixed.
A selection of boot time parameters are were added. These options enable
boot tracing, the One Pass feature, limit the maximum number of CPUs to use,
specify a CPU mask to select CPUs to be used and setup serial console
Improved and extended CPU identification routines. Newer CPUID based
method is now used to determine cache sizes for Intel CPUs for better accuracy
Routines for calculating cache and memory speeds have been reworked for
better accuracy. An overflow problem has been fixed that resulted in no memory
speed being reported for CPUs with large L3 caches.
- Fixed some errors in the crash reporting routines.
- Misc minor fixes and code cleanup.
Version 4.0 28/Mar/2011
- Support for testing with multiple CPUs. All tests except for #11 (Bit Fade) have been multi-threaded. A maximum of 16 CPUs will be used for testing.
CPU detection has been completely re-written to use the brand ID string rather than the cumbersome, difficult to maintain and often out of date CPUID family information.
All new processors will now be correctly identified without requiring code support.
All code related to controller identification, PCI and DMI has been removed. This may be a controversial decision and was not made lightly. The following
are justifications for the decision:
Removing this code also had the unfortunate effect of removing reporting of
correctable ECC errors. The code to support ECC was hopelessly intertwined
the controller identification code. A fresh, streamlined implementation of
ECC reporting is planned for a future release.
- Controller identification has nothing to do with actual testing of memory, the core purpose of MemTest86.
This code needed to be updated with every new chipset. With the ever growing number of chip-sets it is not possible to keep up with the
changes. The result is that new chipsets were more often than not reported in-correctly. In the authors opinion incorrect information is
worse than no information.
- Probing for chipset information carries the risk of making the program crash.
- The amount of code involved with controller identification was quite large, making support more difficult.
- A surprising number of conditions existed that potentially cause problems when testing more than 4 GB of memory. Most if not all of these conditions have been identified and corrected.
A number of cases were corrected where not all of memory was being tested. For most tests the last word of each test block was not tested. In addition an error in the paging code was fixed
that omitted from testing the last 256 bytes of each block above 2 GB.
- The information display has been simplified and a number of details that were not relevant to testing were removed.
- Memory speed measurement has been parallelized for more accurate reporting.
This is a major re-write of the MemTest86 with a large number of minor
bug-fixes and substantial cleanup and re-organization of the code.
Version 3.5 3/Jan/2009
- Limited support for execution with multiple CPUs. CPUs are selected round-robin or sequential for each test.
- Support for detection of additional chipsets. (from MemTest86+ v2.11).
- Additions and corrections for CPU detection including reporting of L3 cache.
- Reworked information display for better readability and new information.
- Abbreviated iterations for first pass.
- Enhancements to memory sizing.
- Misc bug fixes.
Version 3.4 (2/Aug/2007)
- Added an error summary display.
- Added support for additional chipsets. (from MemTest86+ v1.70).
- Additions and corrections for CPU detection.
- Support for memory module information reporting.
- Misc bug fixes.
Version 3.3 (12/Jan/2007)
- Added support for additional chipsets. (from MemTest86+ v1.60)
- Changed Modulo 20 test (#8) to use a more effective random pattern rather than simple ones and zeros.
- Fixed a bug that prevented testing of low memory.
- Added an advanced menu option to display SPD info (only for selected chipsets).
- Updated CPU detection for new CPUs and corrected some bugs.
- Reworked online command text for better clarity.
- Added a fix to correct a Badram pattern bug.
Version 3.2 (11/Nov/2004)
- Added two new, highly effective tests that use random number patterns (tests 4 and 6)
Reworked the online commands:
- Changed wording for better clarity
- Dropped Cache Mode menu
- Updated CPU detection for newer AMD, Intel and Cyrix CPUs
Reworked test sequence:
- Dropped ineffective non cached tests (Numbers 7-11)
- Changed cache mode to "cached" for test 2
- Fixed a bug that did not allow some tests to be skipped
- Added bailout for Bit fade test
- Error reports are highlighted in red to provide a more vivid error indication
- Added support for a large number of additional chipsets (from MemTest86+ v1.30)
- Added an advanced setup feature that with new chipset allows memory timings to be altered from inside MemTest86. (from MemTest86+ v1.30)
- Misc bug-fixes and code cleanup.
Version 3.1a (11/Mar/2004)
- Added processor detection for newer AMD processors
- Added new "Bit Fade" extended test
- Fixed a compile time bug with gcc version 3.x.
- E7500 memory controller ECC support
- Added support for 16bit ECC syndromes
- Option to keep the serial port baud rate of the boot loader
Version 3.0 (22/May/2002) - Provided by Eric Biederman
- Testing of more than 2gb of memory is at last fixed (tested with 6Gb)
- The infrastructure is to poll ecc error reporting chipset registers, and the support has been done for some chipsets.
- Uses dynamic relocation information records to make itself PIC instead of requiring 2 copies of MemTest86 in the binary.
- The serial console code does not do redundant writes to the serial port. Very little slow down at 9600 baud.
- You can press ^l or just l to get a screen refresh, when you are connecting and unconnecting a serial cable.
- Net-booting is working again
- Linux-BIOS support (To get the memory size)
- Many bug-fixes and code cleanup
Version 2.9 (29/Feb/2002)
- The memory sizing code has been completely rewritten. By default MemTest86 gets a memory map from the BIOS that is now used to find available memory. A new online configuration option provides three choices for how memory will be sized, including the old "probe" method. The default mode generally will not test all of memory, but should be more stable. See the Memory Sizing section for details.
- Testing of more than 2gb of memory should now work. A number of bugs were found and corrected that prevented testing above 2gb. Testing with more than 2gb has been limited and there could be problems with a full 4gb of memory.
- Memory is divided into segments for testing. This allow for frequent progress updates and responsiveness to interactive commands. The memory segment size has been increased from 8 to 32mb. This should improve testing effectiveness but progress reports will be less frequent.
- Minor bug fixes
Version 2.8 (18/Oct/2001)
- Eric Biederman reworked the build process making it far simpler and also to produce a network boot-able ELF image.
- Re-wrote the memory and cache speed detection code. Previously the reported numbers were inaccurate for Intel CPU's and completely wrong for the Athlon and Duron.
- Disabled the serial console by default since it was slowing down testing.
- Added CPU detection for Pentium 4
- Minor bug fixes
Version 2.7 (12/Jul/2001)
- Expanded workaround for errors caused by BIOS USB keyboard support to include test #5.
- Re-worked L1 / L2 cache detection code to provide clearer reporting.
- Fixed an obvious bug in the computation of cache and memory speeds.
- Added a menu option to disable the serial console.
- Changed on-line menu to stay in the menu between option selections.
- Fixed bugs in the test restart and redraw code.
- Adjusted code size to fix compilation problems with RedHat 7.1.
- Misc updates to the documentation.
Version 2.6 (25/May/2001)
- Added workaround for errors caused by BIOS USB keyboard support.
- Fixed problems with reporting of 1 GHZ + processor speeds.
- Fixed Duron cache detection.
- Added screen buffer so that menus will work correctly from a serial console. (Code provided by Jani Averbach.)
- The MemTest86 image is now built in ELF format.
Version 2.5 (13/Dec/00)
- Enhanced CPU and cache detection to correctly identify Duron CPU and K6-III 1mb cache.
- Added code to report cache-able memory size.
- Added limited support for parity memory.
- Support was added to allow use of on-line commands from a serial port.
- Dropped option for changing refresh rates. This was not useful and did not work on newer motherboards.
- Improved fatal exception reporting to include a register and stack dump.
- The pass number is now displayed in the error report.
- Fixed a bug that crashed the test when selecting one of the extended tests.
- The error report format was reworked for better clarity and now includes a decimal address in megabytes.
- A new memory move test was added (from Robert Redelmeier's CPU-Burn)
- The test sequence and iterations were modified.
- Fixed scrolling problems with the BadRAM patterns.
- Updated and improved CPU and cache detection.
- Measurement and reporting of memory and cache performance was added.
- All of the test routines were rewritten in assembler to improve both error detection and speed.
- A progress meter was added to show pass and test completion.
- The screen layout was reworked to hopefully be more readable.
- Support for creating BadRAM patterns was added. (Code was provided by Rick van Rein.)
- An error summary option was added to the online commands.
- Added two new address tests.
- Added an on-line command for setting test address range.
- Optimized test code for faster execution (-O3, -funroll-loops and -fomit-frame-pointer).
- Added and elapsed time counter.
- Adjusted menu options for better consistency.
- Fixed a bug in the CPU detection that caused the test to hang or crash with some 486 and Cryrix CPU's
- Added CPU detection for Cyrix CPU's
- Extended and improved CPU detection for Intel and AMD CPU's
- Added a compile time option (BIOS_MEMSZ) for obtaining the last memory address from the BIOS. This should fix problems with memory sizing on certain motherboards. This option is not enabled by default. It may be enabled by default in a future release.
- Added new Modulo-20 test algorithm.
- Added a 32 bit shifting pattern to the moving inversions algorithm.
- Created test sections to specify algorithm, pattern, cache and refresh rate.
- Improved test progress indicators.
- Created pop-up menus for configuration.
- Added menu for test selection.
- Added CPU and cache identification.
- Added a "bail out" feature to quit the current test when it does not fit the test selection parameters.
- Re-arranged the screen layout and colors.
- Created local include files for I/O and serial interface definitions rather than using the sometimes incompatible system include files.
- Broke up the "C" source code into four separate source modules.
- Some additional changes were made to fix obscure memory sizing problems.
- The 4 bit wide data pattern was increased to 8 bits since 8 bit wide memory chips are becoming more common.
- A new test algorithm was added to improve detection of data pattern sensitive errors.
- Changes to the memory sizing code to avoid problems with some motherboards where MemTest86 would find more memory than actually exists.
- Added support for a console serial port. (Thanks to Doug Sisk)
- On-line commands are now available for configuring MemTest86 on the fly (see On-line Commands).
- Scrolling of memory errors is now provided. Previously, only one screen of error information was displayed.
- MemTest86 can now be booted from any disk via lilo.
- Detection of up to 4gb of memory has been fixed is now enabled by default. This capability was clearly broken in v1.2a and should work correctly now but has not been fully tested (4gb PC's are a bit rare).
- The maximum memory size supported by the motherboard is now being calculated correctly. In previous versions there were cases where not all of memory would be tested and the maximum memory size supported was incorrect.
- For some types of failures the good and bad values were reported to be same with an Xor value of 0. This has been fixed by retaining the data read from memory and not re-reading the bad data in the error reporting routine.
- APM (advanced power management) is now disabled by MemTest86. This keeps the screen from blanking while the test is running.
- Problems with enabling & disabling cache on some motherboards have been corrected.